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International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 Transmission Line Fault Analysis using Bus Impedance Matrix Method Prajakta V. Dhole1 Farina S. Khan1 First Year Engineering Department, JSPM's Imperial College of Engg. & Research, Wagholi, Pune Savitribai Phule Pune University, Pune, India First Year Engineering Department, JSPM's Imperial College of Engg. & Research, Wagholi, Pune Savitribai Phule Pune University, Pune, India Abstract -- The fault analysis is done for the three phase symmetrical fault and the unsymmetrical faults. The unsymmetrical faults include single line to ground, line to line and double line to ground fault. The method employed is bus impedance matrix which has certain advantages over thevenin’s equivalent method. The advantage of this approach over conventional method is to make the analysis of three typical un-symmetrical faults, namely single-line-to-ground fault, line-to-line fault and double-line-to-ground fault more unified. So it is unnecessary to cumbersomely connect three sequence networks when calculating the fault voltages at each bus and fault currents flowing from one bus to its neighboring bus. Keywords- Bus impedance matrix; fault analysis; fault impedance; thevenin’s equivalent. 3. Line-to-line fault (LL) 4. Double line-to-ground fault (DLG) The most common type of faults by far is the SLG fault, followed in frequency of occurrence by the LL fault, DLG fault, and three-phase fault. Out of the above four faults, two are of the line-toground faults. Most of these occur as a result of insulator flashover during electrical storms. The balanced threephase fault is the rarest in occurrence and the least complex in so far as the fault current calculations are concerned. The other three unsymmetrical faults will require the knowledge and use of symmetrical components. Unsymmetrical faults cause unbalanced currents to flow in the system. The method of symmetrical components is a very powerful tool which makes the calculations of unsymmetrical faults almost as easy as the calculations of a three-phase fault. To analyze un-symmetrical faults, one needs to develop positive-, negative-, and zero-sequence networks of the power system under study, based on which one further need to work out the impedance of three thevenin equivalent circuits as viewed from faulty point. Then the positive-, negative- and zero-sequence components of phase-a faulty-point-to-ground current can be calculated. To calculate three-phase currents flowing from one bus to its neighboring bus and three-phase voltages at each bus, one needs to connect three sequence networks uniquely for each type of fault. This may make circuit drawing very cumbersome. Furthermore by using the network with three sequence networks connected, it is impossible to appreciate the impedance matrix approach to calculate the sequence voltage at each bus when fault occurs. To overcome these two drawbacks, paper [1] introduces a new approach to unify the analysis of three typical unsymmetrical faults, namely single-line-to-ground fault, line-to-line fault and double-line-to-ground fault. This new method allows the analysis of three typical un-symmetrical faults to share all steps except one. The only different step is how to calculate the positive-, negative-, and zerosequence components of phase-a-to-ground fault current at faulty point. It also makes impedance matrix approach more understandable when used to calculate the sequence voltages at each bus. I. INTRODUCTION The steady state operating mode of a power system is balanced 3-phase ac. However due to sudden external or internal changes in the system, this condition is disrupted. When the insulation of the system fails at one or more points or a conducting object comes in contact with a live point, a short circuit or fault occurs. A fault involving all the three phases is known as symmetrical (balanced) fault while one involving only one or two phases is known as unsymmetrical fault. Majority of the faults are unsymmetrical. Fault calculations involve finding the voltage and current distribution throughout the system during the fault. It is important to determine the values of system voltages and currents during fault conditions so that the protective devices may be set to detect the fault and isolate the faulty portion of the system. II. FAULTS IN A THREE PHASE SYSTEM 1. 2. Symmetrical three-phase fault Single line-to-ground fault (SLG) IJERTV4IS030919 www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) 948 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 All the above four faults (1, 2, 3, 4) are being solved using the bus impedance matrix. Fig. 3. Fig. 1. Double line to ground fault Single line to ground fault III. BUS IMPEDANCE MATRIX METHOD We can work out a universal representation of all three typical un-symmetrical faults. This representation is valid with the imposition of different fault conditions for each typical un-symmetrical fault, such as for the single-line-toground fault, such as for the single-line-to-ground fault, the fault conditions being Vka=ZfIfa, IfbIfc0. Fig. 2. Line to line fault In the following formulation, per-unit system is adopted. Zero-sequence voltage at each bus contributed by equivalent current source is determined by Y11 0 Y12 0 .. Y1k 0 .. Y1n 0 V1f 0 0 0 0 0 0 0 Y21 Y22 .. Y2k .. Y2n V2f 0 : : .. : .. : : : = Y 0 Y 0 .. Y 0 .. Y 0 V 0 -Ifa0 k1 k2 kk kn kf : : : : : : : : 0 0 0 0 0 0 Yn1 Yn2 .. Ynk .. Ynn Vnf where Y11 0 0 Y21 0 Y = : Y 0 k1 : 0 Yn1 IJERTV4IS030919 Y12 0 .. Y1k 0 .. 0 Y22 : .. .. 0 Y2k : .. .. 0 Yk2 : .. : 0 Y kk : .. : 0 Yn2 .. 0 Ynk .. www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) Y1n 0 0 Y2n : 0 Ykn : 0 Ynn 949 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 So is the admittance matrix for the sub-transient or transient zero-sequence network. 0 0 V1f 0 -Z1k I fa 0 0 0 V2f -Z 2k I fa : : = V 0 -Z 0 I 0 kf kk fa : : 0 0 0 Vnf -Z nk I fa Then V1f 0 Y 0 0 11 V2f Y21 0 : = : V 0 Y 0 kf k1 : : 0 0 Vnf Yn1 Y12 0 .. Y1k 0 0 0 Y22 : .. Y2k .. : Yk2 0 : .. Y kk0 : : Yn2 0 .. Ynk 0 .. Y1n 0 .. Y2n 0 .. : .. Ykn 0 : : .. Ynn 0 0 0 : 0 = Z 0 -I fa : 0 0 Z11 0 Z21 = : Z 0 k1 : 0 Zn1 In a similar way, positive-sequence voltage at each bus contributed by equivalent current source as is determined by Y111 1 Y21 : Y 1 k1 : 1 Yn1 Where, 0 Z11 0 Z21 0 : Z = 0 Z k1 : 0 Zn1 0 0 : 0 -Ifa : 0 0 0 Z12 .. Z1k Z220 .. Z2k0 : .. : Zk20 .. Z kk0 : : : Zn20 .. Znk0 0 .. Z1n .. Z2n0 .. : .. Zkn0 : : .. Znn0 0 Z12 .. 0 Z1k .. Z220 : .. .. Z2k0 : .. .. Zk20 : .. : 0 Z kk : .. : Zn20 .. Znk0 .. 0 Z1n Z2n0 : Zkn0 : Znn0 Y121 .. Y1k1 .. Y1n1 V1f1 0 Y221 .. Y2k1 .. Y2n1 V2f1 0 : .. : .. : : : = 1 Yk21 .. Y kk1 .. Ykn1 Vkf1 -Ifa : : : : : : : Yn21 .. Ynk1 .. Ynn1 Vnf1 0 This gives 1 V1f1 Z11 1 1 V2f Z21 : : = V 1 Z1 kf k1 : : 1 1 Vnf Zn1 1 Z12 .. 1 Z1k Z221 : .. .. Z2k1 : Zk21 : .. Z kk1 : : Zn21 .. Znk1 1 .. Z1n .. Z2n1 .. : .. Zkn1 : : .. Znn1 1 1 0 -Z1k I fa 0 1 1 -Z 2k I fa : : 1 = 1 1 -I fa -Z kk I fa : : 1 1 0 -Z I nk fa If pre-fault current is ignored, then the pre-fault voltage at each bus is the same and equal to that at fault bus k before fault occurs, which is assumed to be Vf. So the positive sequence voltage at each bus when fault occurs can be written as follows. IJERTV4IS030919 www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) 950 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 V1f1 V11 V1f1 V -Z1k1 Ifa1 1 1 1 f 1 1 V2f V2 V2f Vf -Z2k Ifa : : : : : = + = + V 1 V 1 V 1 Vf -Z 1 I1 kf k kf kk fa : : : : : 1 1 1 Vf 1 1 Vnf Vn Vnf -Znk Ifa Item Base MVA Voltage Rating X1 X2 X0 G1 G2 T1 T2 TL1 TL2 TL3 100 100 100 100 100 100 100 20 kV 20 kV 20/220 kV 20/220 kV 220 kV 220 kV 220 kV 0.15 0.15 0.10 0.10 0.125 0.15 0.25 0.15 0.15 0.10 0.10 0.125 0.15 0.25 0.05 0.05 0.10 0.10 0.30 0.35 0.7125 Vf -Z1k1 Ifa1 1 1 Vf -Z2k Ifa : = V -Z 1 I1 f kk fa : 1 1 Vf -Znk Ifa In a similar way, the negative-sequence voltage at each bus can be computed by 2 2 V1f 2 -Z1k I fa 2 2 2 V2f -Z 2k I fa : : = V 2 -Z 2 I 2 kk fa kf : : 2 2 2 Vnf -Z nk I fa 2 Z11 2 Z21 : Z 2 = 2 Z k1 : 2 Zn1 TABLEI. Fig. 4. Single line diagram 1 IV. MATHEMATICAL ANALYSIS A. Sequence impedance networks Firstly let us obtain the sequence impedance networks. From the data given in table 4.1 the following positive, negative and zero sequence impedance networks are obtained in fig.4.6, 4.7 and 4.8 respectively. 2 2 2 Z12 .. Z1k .. Z1n Z222 .. Z2k2 .. Z2n2 : .. : .. : Zk22 .. Z kk2 .. Zkn2 : : : : : Zn22 .. Znk2 .. Znn2 POWER SYSTEM NETWORK PARAMETERS Fig. 5. IJERTV4IS030919 Positive Sequence impedance network www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) 951 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 Fig. 9. Fig. 6. 2 1 Ybus Ybus Fig. 7. Positive Sequence admittance network Negative Sequence impedance network j6.667 -j18.667 j8 j8 -j16 j4 j6.667 j4 -j10.667 Zero Sequence impedance network Fig. 10. Zero Sequence admittance network j3.3333 j2.8571 -j8.690 Y = j3.3333 -j14.7368 j1.4035 j2.8571 j1.4035 -j4.2606 0 bus B. IMPEDANCE MATRICES The impedance matrices are obtained from the admittance matrices. Z1bus Fig. 8. IJERTV4IS030919 Positive Sequence admittance network = j0.1450 = j0.1050 j0.1300 j0.1050 j0.1450 j0.1200 j0.1300 j0.1200 j0.2200 j0.1820 Z0bus = j0.0545 j0.1400 j0.0545 j0.0864 j0.0650 j0.1400 j0.0650 j0.3500 Z2bus www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) 952 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 C. Single Line To Ground Fault At Bus 3 Through A Fault Impedance Of J0.1 When single line to ground fault occurs, the sequence components of fault current at bus three are given by I1f3 I2f3 I0f3 = Vk (0) Z +Z2kk +Z0kk +3Zf 1 kk V3 (0) = 1 2 0 Z33 +Z33 +Z33 +3Zf = = 100 j0.22+j0.22+j0.35+3(j0.1) 1 0 0 j1.09 At bus 1 0 0 Vf10 0-Z13 I3 0-j0.14(-j0.9174) 0.1284 1 1 1 1 = = 0.8807 V = V (0)-Z 13I 3 f1 1 1-j0.13(-j0.9174) 2 2 Vf12 0-Z13 I3 0-j0.13(-j0.9174) 0.1193 At bus2 Vf20 0-Z023I30 1 1 1 1= Vf2 = V2 (0)-Z23I3 Vf22 0-Z223I32 0-j0.065(-j0.9174) 1-j0.120(-j0.9174) = 0-j0.120(-j0.9174) 0.0596 0.8899 0.1101 Vf30 0-Z023I30 0-j0.35(-j0.9174) 1 1 = 1 1 = Vf3 = V3 (0)-Z33I3 1-j0.22(-j0.9174) 2 2 Vf32 0-Z33 I3 0-j0.22(-j0.9174) 0.3211 0.7982 0.2018 At bus3 The voltages during fault are = -j0.9174 p.u. At bus 1 The fault current is Iaf3 1 1 b 2 If3 = 1 a Icf3 1 a 0 1 If3 a I 0f3 a 2 I0f3 Vf1a 1 1 b 2 Vf1 = 1 a Vf1c 1 a 1 Vf10 1 1 2 a Vf11 = 1 a a 2 Vf12 1 a 1 a a 2 0.1284 0.8807 0.1193 1 a a 2 0.0596 0.8899 0.1101 1 a a 2 0.3211 0.7982 0.2018 0.63300 0 1.0046 120.45 1.0046120.450 = 3I0f3 = 0 0 At bus 2 Vf2a 1 1 b 2 Vf2 = 1 a Vf2c 1 a 3(-j0.9174) = 0 0 1 Vf20 1 1 2 a Vf21 = 1 a a 2 Vf22 1 a 0.720700 = 0.9757 117.430 0.9757 117.430 -j2.7522 = 0 0 At bus 3 2.7523 900 = 0 0 Vf3a 1 1 b 2 Vf3 = 1 a Vf3c 1 a 1 Vf30 1 1 2 a Vf31 = 1 a a 2 Vf32 1 a The symmetrical components of voltages during fault at buses 1, 2 and 3 IJERTV4IS030919 www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) 953 International Journal of Engineering Research & Technology (IJERT) ISSN: 2278-0181 Vol. 4 Issue 03, March-2015 0.275200 0 = 1.0647 125.56 1.0647 125.560 V. VI. [1] CONCLUSION [2] This paper presents a method to tackle typical unsymmetrical faults. It is found that the bus impedance matrix method involves comparatively less computations than the thevenin’s equivalent method. The proposed approach has another advantage over traditional method that it is more intuitive when matrix approach is adopted to tackle a fault problem. IJERTV4IS030919 REFERENCES Daming Zhang,”An alternative approach to analyze unsymmetrical faults in power system”. TENCON 2009, from ieeexplore. B. R. Gupta, Power System Analysis and Design, published by S. Chand and Company Ltd., p.265. www.ijert.org (This work is licensed under a Creative Commons Attribution 4.0 International License.) 954